In recent years, as various video apparatuses and communication apparatuses are introduced on the market, semiconductor integrated circuit devices for use in those apparatuses are increasingly developed. The scales of the semiconductor integrated circuit devices are significantly increased, leading to a large demand for higher performance, higher speed, more functions, smaller size, lower power consumption and the like.
In such circumstances, various electronic apparatuses, when transmitting a signal from the inside to the outside of a semiconductor integrated circuit, employ various types of D/A converters, depending on the application (e.g., a control system, a display system, a video system, an audio system, a communication system, etc.), so as to convert a digital signal into an analog signal. For example, in LSIs for video applications, communication applications and the like, a current steering D/A converter that can perform a high-speed operation of several tens of megahertz to several hundreds of megahertz or several gigahertz is essentially required. Also, in order to achieve a higher-performance video apparatus or communication apparatus, a D/A converter having a higher resolution and a higher accuracy is required, and therefore, a higher-performance D/A converter is strongly desired.
An exemplary conventional D/A converter will be described as follows.
FIG. 11 is a diagram showing a circuit configuration of a conventional current steering D/A converter. The D/A converter 400 of FIG. 11 is an 8-bit D/A converter that comprises a plurality of current sources (IS1, IS2 and IS3-1 to IS3-63), a plurality of differential switches (SW1, SW2 and SW3-1 to SW3-63), a bias circuit 401, and a decoder circuit 402.
The differential switches (SW1, SW2 and SW3-1 to SW3-63) have different transistor sizes, but have the same configuration, i.e., each comprises two P-channel transistors (P-channel transistors 406 and 407), as shown in FIG. 11.
Also, the current sources have different transistor sizes, but have the same configuration.
The current source IS1 is a 1-LSB current source, the current source IS2 is a 2-LSB current source, and the current sources IS3-1 to IS3-63 are each a 4-LSB current source. Combinations of these current sources represent eight bits, i.e., 256 levels of gray. The currents of these current sources are determined by a first bias voltage VB1 and a second bias voltage VB2 generated in the bias circuit 401. The differential switches (SW1, SW2 and SW3-1 to SW3-63) are controlled in accordance with decoded signals D1, D2 and D3-1 to D3-63 obtained by decoding input digital codes IN0 to IN7 by the decoder circuit 402 and their inverted decoded signals D1B, D2B and D3-1B to D3-63B, respectively. Thereby, the differential switches SW1, SW2 and SW3-1 to SW3-63 switch the destinations of currents from the respective corresponding current sources between an analog non-inversion output terminal OUT and an analog inversion output terminal NOUT.
Thereafter, the currents from the current sources are added at the analog non-inversion output terminal OUT or the analog inversion output terminal NOUT, so that an analog output current corresponding to the input digital codes is output. The analog output current is converted into a voltage by a resistor 403-1 or a resistor 403-2 for current-voltage conversion, so that an analog output voltage corresponding to the input digital codes is obtained.
The current sources IS1, IS2 and IS3-1 to IS3-63 each include two P-channel transistors (P-channel transistors 404 and 405) that are cascade-connected. The transistor to the gate terminal of which VB1 is applied is a transistor (hereinafter referred to as a current source transistor) for determining a current value, and the transistor to the gate terminal of which VB2 is applied is a transistor (hereinafter referred to as a cascode transistor) that is cascade-connected to the current source transistor so as to improve the output impedance of the current source (i.e., improve the constant-current characteristics).
In general, if a cascode transistor is connected to a current source transistor, the output impedance of the current source is about gm/gds times as large as the output impedance of the current source transistor (gm and gds are of the cascode transistor).
Typically, both the back-gate terminals of the current source transistor and the cascode transistor are connected to a power source VDD.
The bias circuit 401 comprises a first bias transistor 401a, a second bias transistor 401b, and a current source that are connected as shown in FIG. 11. The bias circuit 401 outputs the first bias voltage VB1 and the second bias voltage VB2. In this case, the back-gate terminals of the first bias transistor 401a and the second bias transistor 401b in the bias circuit 401 that are paired with the current source transistor and the cascode transistor, respectively, of each of the current sources IS1, IS2 and IS3-1 to IS3-63 into current mirror circuits, are connected to the power source VDD.
Incidentally, representative characteristics of a D/A converter generally include linearity characteristics and distortion characteristics.
In the D/A converter 400, the relative accuracy and output impedance of a current source need to be improved so as to achieve more accurate linearity and lower distortion.
Firstly, in order to increase the accuracy of the D/A converter 400, the relative accuracy of the output current of each current source needs to be improved. In general, the relative accuracy (mismatch) of the threshold (Vt) and the current of a transistor are proportional to 1/√[L×W] (L: the gate length, W: the gate width). Therefore, the current source transistor is conventionally designed to have a larger area so that variations therein are reduced, so as to improve the relative accuracy of the output current.
Also, conventionally, in order to increase the output impedances of the current sources IS1, IS2 and IS3-1 to IS3-63, the gm/gds of the cascode transistor is increased, thereby improving the output impedance of the whole current source. Specifically, in order to increase the gm (transconductance) of the cascode transistor, and to decrease the gds (drain conductance) of the cascode transistor, the W/L ratio is increased while increasing the L of the cascode transistor, thereby increasing the size of the cascode transistor.
Also, a mismatch between the pair transistors included in the differential switch may be responsible for a deterioration in distortion characteristics. Therefore, such a mismatch is conventionally suppressed by increasing the sizes of the pair transistors.
Incidentally, it has been disclosed that, as a method for reducing variations in threshold and current of a transistor, a forward body bias is applied to the back-gate terminal of the transistor (see, for example, Non-Patent Document 1). In this case, as a means for generating the forward body bias voltage, a method for causing a current to flow through a parasitic diode between the source terminal and the back-gate terminal of the transistor has been disclosed (see, for example, Non-Patent Document 1 and Patent Document 1).
Also, a means for applying a forward body bias to the back-gate terminals of the differential pair transistors of a differential amplifier to improve the gm of each of the differential pair transistors and reduce the gds thereof (particularly, suppress the short-channel effect), and as a result, increase the gain (gm/gds) of the differential amplifier, has been disclosed (see, for example, Patent Document 2).
Also, it has been disclosed that, as a method for applying a forward body bias, a bias current to be extracted from the well of a MOS transistor is determined, and the determined bias current is extracted from the well, thereby applying a bias from an external circuit to the well (see, for example, Patent Document 3).    Non-Patent Document 1: Y. Komatsu et al., “Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias”, IEICE TRANSACTIONS on Electronics, 2007 vol. E90-C, No. 4, p. 692-698    Patent Document 1: U.S. Pat. No. 6,864,539    Patent Document 2: U.S. Pat. No. 6,218,892    Patent Document 3: Japanese Unexamined Patent Application Publication No. 2005-311359